Method and apparatus for reducing the processing rate of a chip-level equalization receiver

ABSTRACT

A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 11/210,591 filed Aug. 24, 2005, which issued as U.S. Pat. No. 7,116,705 on Oct. 3, 2006, which claims the benefit of U.S. Provisional Application No. 60/625,870 filed Nov. 8, 2004, which are incorporated by reference as if fully set forth.

FIELD OF THE INVENTION

The present invention relates to a code division multiple access (CDMA) receiver. More particularly, the present invention relates to a method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in the CDMA receiver.

BACKGROUND

Chip-level equalizers are suitable candidates for CDMA receivers, such as those used in wireless transmit/receive units (WTRUs) and base stations. A normalized least mean square (NLMS)-based CLE receiver offers superior performance for high data rate services such as high speed downlink packet access (HSDPA) over a Rake receiver. A typical NLMS receiver consists of an equalizer filter and an NLMS algorithm. The equalizer filter is typically a finite impulse response (FIR) filter.

The NLMS algorithm is used as the tap coefficients generator. It generates appropriate tap coefficients used by the equalizer filter and updates them appropriately and iteratively in a timely basis. Typically, tap coefficients generation includes the error signal computation, vector norm calculation and leaky integration to generate and update the tap coefficients.

The high complexity of the CLE is due to the over-sampling processing in the CLE. A typical CLE includes equalizer filtering, tap-weight vector updating, vector norm square computing, or the like, which all operate at two or more times the chip rate. Two times the chip rate over-sampling processing induces twice as much complexity as the chip rate non-over-sampling processing in the equalizer filter.

SUMMARY

The present invention is related to a method and apparatus for reducing the processing rate when performing CLE in a CDMA receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate, where M is a positive integer. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed understanding of the invention may be had from the following description, given by way of example and to be understood in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram of an exemplary CDMA receiver configured in accordance with a first embodiment of the present invention;

FIG. 2 is a block diagram of an exemplary CDMA receiver configured in accordance with a second embodiment of the present invention;

FIGS. 3A and 3B, taken together, are a block diagram of an exemplary CDMA receiver configured in accordance with a third embodiment of the present invention; and

FIG. 4 is a flow diagram of a process for implementing non-over-sampling processing in a CDMA receiver in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments will be described with reference to the drawing figures where like numerals represent like elements throughout.

Hereafter, the terminology “WTRU” includes but is not limited to a user equipment (UE), a mobile station, a laptop, a personal data assistant (PDA), a fixed or mobile subscriber unit, a pager, or any other type of device capable of operating in a wireless environment. When referred to hereafter, the terminology “base station” includes but is not limited to an access point (AP), a Node-B, a site controller or any other type of interfacing device in a wireless environment.

The features of the present invention may be incorporated into an integrated circuit (IC) or be configured in a circuit comprising a multitude of interconnecting components.

Hereafter, the present invention will be explained with reference to an NLMS algorithm. However, it should be noted that any type of adaptive equalization or filtering, such as least mean square (LMS), Griffith's algorithm, channel estimation based NLMS (CE-NLMS), and other iterative or recursive algorithms may be used.

FIG. 1 is a block diagram of an exemplary CDMA receiver 100 configured in accordance with a first embodiment of the present invention. The CDMA receiver 100 includes at least one antenna 102, a sampler 104, a serial-to-parallel (S/P) converter 106, two multipath combiners 108A, 108B, an over-sample combiner 110 and a 1× chip rate non-over-sample processing NLMS equalizer 112. The NLMS equalizer 112 includes an equalizer filter 114 and a taps coefficients generator 116.

Signals are received by the antenna 102 and are sampled by the sampler 104 at twice the chip rate. The sampler 104 outputs a sample data stream 105, which is split into an odd sample data stream 107A and an even sample data stream 107B by the S/P converter 106. Therefore, the chip rate of signals output by the S/P converter 106 is one times (1×) the chip rate.

The even and odd sample data streams 107A, 107B are fed into respective ones of the multipath combiners 108A, 108B. Multipath is the signal spread in the time domain due to reflection of signal from objects. The same signal may arrive at the receiver at different times, (due to reflection), either early or late, (depending on the reflection distances), and with different amplitudes and phases due to fading. The multipath combiners 108A, 108B collect and combine an original signal with their delayed spread signal (multipath signal or delayed replicates) to improve the reception quality. Each of the sample data streams 107A, 107B has one sample stream and one or more delayed sample streams. The number of delayed sample data streams depends on the number of multipaths that the original signal experienced.

The multipath combiners 108A, 108B combine the multipath or delayed replicates of the signal data streams 107A, 107B. Maximum ratio combining (MRC) may be used for multipath combining. The multipath combined signal data streams 109A, 109B output by the respective multipath combiners 108A, 108B are then fed to an over-sample combiner 110.

The over-sample combiner 110 combines the multipath combined signal streams 109A, 109B and produces one combined sample data stream 111 at one times (1×) the chip rate. The combined sample stream 111 is fed into the equalizer filter 114 and the taps coefficients generator 116.

A matched filter (MF) may be used as the multipath combiners 108A, 108B and the over-sample combiner 110. The parameters {right arrow over (x)}_(n) ^(i,o), {right arrow over (x)}_(n) ^(i,e), and H^(i,o), H^(i,e) are denoted as a received signal vector and a channel response matrix for odd and even over-sampled sequences, respectively. The vector {right arrow over (x)}_(n,co) is denoted as a combined signal vector after the multipath and over-sample combining. Assuming that a matched filter is used for multipath and over-sample combining, the combined signal can be expressed as follows: {right arrow over (x)} _(n,co) =H ^(1,o) ^(H) {right arrow over (x)} _(n) ^(1,o) +H ^(1,e) ^(H) {right arrow over (x)} _(n) ^(1,e) +H ^(2,o) ^(H) {right arrow over (x)} _(n) ^(2,o) +H ^(2,e) ^(H) {right arrow over (x)} _(n) ^(2,e).  Equation (1)

After the signal combining is performed, one improved signal stream 111 is formed and is fed to the equalizer filter 114 to perform equalization to remove interference such as inter-symbol interference (ISI) and multiple access interference (MAI). The equalizer filter 114 is preferably a finite impulse response (FIR) filter comprising a tap-delay line with tap coefficients of L taps. The NLMS equalizer 112 may be described in terms of weight updates as follows:

$\begin{matrix} {{{\overset{\rightarrow}{w}}_{{n + 1},{co}} = {{\alpha \cdot {\overset{\rightarrow}{w}}_{n,{co}}} + {\mu\frac{{\overset{\rightarrow}{x}}_{n,{co}}^{*}}{x_{n,{co}}}\left( {{d\lbrack n\rbrack} - {{\overset{\rightarrow}{x}}_{n,{co}}^{T}{\overset{\rightarrow}{w}}_{n,{co}}}} \right)}}},} & {{Equation}\mspace{14mu}(2)} \end{matrix}$ where {right arrow over (w)}_(n,co) is the tap-weight vector and d[n] is the reference signal at time n.

In accordance with the present invention, the equalizer filter 114 operates at 1× chip rate and does not have over-sampling processing. Therefore, the number of taps of the equalizer filter 114 is smaller than that is required in a prior art equalizer filter with 2× chip rate processing. The equalizer filter 114 requires only half of the number of taps in the 2× chip rate equalizer filter.

The tap coefficients generator 116 includes multipliers 118, 124, an adder 130, a serial-to-parallel (S→P) to vector converter 122, a vector accumulator 126, a correction term generator 128 and a chips accumulator 132. The output from the equalizer filter 114 is descrambled via the multiplier 118. The output of the multiplier 118 is accumulated by the chips accumulator 132 for a predetermined period, (e.g., for chips equal to a common pilot channel (CPICH) despreading factor). The accumulated result output by the chips accumulator 132 is subtracted from a reference pilot signal 129 via the adder 130 to generate an error signal 131, represented by a variable e, which is used by the correction term generator 128 to generate correction terms 134.

The combined input sample data stream 111 is converted to length L vectors by the S→P to vector converter 122 and descrambled by the multiplier 124. The descrambled input vectors are accumulated for a predetermined period, (e.g., for chips equal to a CPICH despreading factor) by the vectors accumulator 126 to generate update vectors 127. The update vectors 127 are forwarded to the correction term generator 128. To generate correction terms for tap coefficient updates, the inputs for μ_(p), e, X_(ud) are required. μ_(p) is the step size. e is the error signal which is the differential signal between an equalized signal and a reference signal, which typically is used in the form of a pilot signal. X_(ud) is the received signal after descrambling and despreading. ∥X_(ud)∥² is the norm of the descrambled and despread signal X_(ud). Equation (2) is used for iteration algorithm and tap coefficient updates.

The correction term generator 128 may generate the correction terms 134 based on the correction term

$\mu_{P} \cdot e \cdot \frac{X_{ud}^{*}}{{X_{ud}}^{2}}$ which is added, in the equalizer filter 114, to the filter coefficients of the previous iteration to generate updated filter coefficients for the next iteration.

Alternatively, the correction term generator 128 may generate the correction terms 134 based on the correction term

$\mu_{P} \cdot e \cdot {\frac{X_{ud}^{*}}{{{X_{ud}}^{2} + \eta}\;}.}$ The variable η is a relatively small number that is used to improve the numerical properties and prevent the fixed-point computation from overflow when the correction term is generated.

FIG. 2 is a block diagram of an exemplary CDMA receiver 200 configured in accordance with a second embodiment of the present invention. The CDMA receiver 200 includes two antennas 202A, 202B, two samplers 204A, 204B, two S/P converters 206A, 206B, four multipath combiners 208A, 208B, 208C, 208D, two over-sample combiners 210A, 210B, an antenna diversity combiner 212 and the 1× chip rate non-over-sample processing NLMS equalizer 112 described above with respect to FIG. 1.

Signals are received by the antennas 202A, 202B and are respectively sampled by the samplers 204A, 204B at twice (2×) the chip rate. The sampler 204A outputs a sample data stream 205A, which is split into an odd sample data stream 207A and an even sample data stream 207B by the S/P converter 206A at one times (1×) the chip rate. The sampler 204B outputs a sample data stream 205B, which is split into an odd sample data stream 207C and an even sample data stream 207D by the S/P converter 206B at one times (1×) the chip rate.

The odd sample data stream 207A and the even sample data stream 207B are fed into respective ones of the multipath combiners 208A, 208B. The multipath combiners 208A, 208B respectively combine the multipath or delayed replicates of the signal data streams 207A, 207B. Maximum ratio combining (MRC) may be used for multipath combining. The multipath combined signal data streams 209A, 209B are output by the respective multipath combiners 208A, 208B at one times (1×) the chip rate and are then fed to an over-sample combiner 210A. The over-sample combiner 210A combines the multipath combined signal streams 209A, 209B and produces a first combined sample data stream 211A at one times (1×) the chip rate.

The odd sample data stream 207C and the even sample data stream 207D are fed into respective ones of the multipath combiners 208C, 208D. The multipath combiners 208C, 208D respectively combine the multipath or delayed replicates of the signal data streams 207C, 207D. MRC may be used for multipath combining. The multipath combined signal data streams 209C, 209D are output by the respective multipath combiners 208C, 208D at one times (1×) the chip rate and are then fed to an over-sample combiner 210B. The over-sample combiner 210B combines the multipath combined signal streams 209C, 209D and produces a second combined sample data stream 211B at one times (1×) the chip rate.

The combined sample data stream 211A and 211B are combined by the antenna diversity combiner 212, and the combined output 214 of the antenna diversity combiner 212 is fed into the equalizer filter 114 and the taps coefficients generator 116 of the 1× chip rate non-over-sample processing NLMS equalizer 112.

FIGS. 3A and 3B, taken together, are a block diagram of an exemplary CDMA receiver 300 configured in accordance with a third embodiment of the present invention. The third embodiment is an extension of the first and second embodiments to N antennas and M× oversampling, where N and M are positive integers. The CDMA receiver 300 includes N antennas 302 ₁-302 _(N), N samplers 304 ₁-304 _(N), N S/P converters 306 ₁-306 _(N), (i.e., splitters), N×M multipath combiners 308 ₁₁-308 _(NM), N over-sample combiners 310 ₁-310 _(N), an antenna diversity combiner 312 and the 1× chip rate non-over-sample processing NLMS equalizer 112 described above with respect to FIG. 1.

Signals are received by the antennas 302 ₁-302 _(N) and are respectively sampled by the samplers 304 ₁-304 _(N) at M times (M×) the chip rate, (i.e., 1^(st) sample sequence, 2^(nd) sample sequence, . . . , the Mth sample sequence).

In response to receiving a signal from the antenna 302 ₁, the sampler 304 ₁ generates a sample data stream 305 ₁ which is split into M sample sequences 307 ₁₁-307 _(1M) by the S/P converter 306 ₁, (i.e., a splitter), at one times (1×) the chip rate. The multipath components of each respective M sample sequence 307 ₁₁-307 _(1M) are combined by a respective one of the multipath combiners 308 ₁₁-308 _(1M) which generates a respective over-sampled stream 309 ₁₁-309 _(1M) that is fed to the over-sample combiner 310 ₁. The over-sample combiner 310 ₁ combines the over-sampled streams 309 ₁₁-309 _(1M) into a combined over-sampled stream 311 ₁ which is then fed to the antenna diversity combiner 312.

In response to receiving a signal from the antenna 302 ₂, the sampler 304 ₂ generates a sample data stream 305 ₂ which is split into M sample sequences 307 ₂₁-307 _(2M) by the S/P converter 306 ₂, (i.e., a splitter), at one times (1×) the chip rate. All multipath components of each respective M sample sequence 307 ₂₁-307 _(2M) are combined by a respective one of the multipath combiners 308 ₂₁-308 _(2M) which generates a respective over-sampled stream 309 ₂₁-309 _(2M) that is fed to the over-sample combiner 310 ₂. The over-sample combiner 310 ₂ combines the over-sampled streams 309 ₂₁-309 _(2M) into a combined over-sampled stream 311 ₂ which is fed to the antenna diversity combiner 312.

In response to receiving a signal from the antenna 302 _(N), the sampler 304 _(N) generates a sample data stream 305 _(N) which is split into M sample sequences 307 _(N1)-307 _(NM) by the S/P converter 306 _(N), (i.e., a splitter), at one times (1×) the chip rate. All multipath components of each respective M sample sequence 307 _(N1)-307 _(NM) are combined by a respective one of the multipath combiners 308 _(N1)-308 _(NM) which generates a respective over-sampled stream 309 _(N1)-309 _(NM) that is fed to the over-sample combiner 310 _(N). The over-sample combiner 310 _(N) combines the over-sampled streams 309 _(N1)-309 _(NM) into a combined over-sampled stream 311 _(N) which is then fed to the antenna diversity combiner 312.

The antenna diversity combiner 312 combines the combined over-sampled streams 311 ₁-311 _(N) into an antenna diversity sample data stream 314 at chip rate. The antenna diversity sample data stream 314 is input to the equalizer filter 114 and the taps coefficients generator 116 of the 1× chip rate non-over-sample processing NLMS equalizer 112.

The foregoing description is related to a despread pilot-directed receiver. As an alternative, the receiver may be a non-despread pilot-directed receiver. In such case, no accumulation of the descrambled samples is performed.

FIG. 4 is a flow diagram of a process 400 including method steps for implementing non-over-sampling processing in accordance with the present invention. In step 402, signals are received using N antennas 302 ₁-302 _(N), where N is a positive integer. In step 404, a sample data stream 305 ₁-305 _(N) is generated for each of the N antennas 302 ₁-302 _(N) at M times the chip rate based on the received signals, where M is a positive integer. In step 406, each sample data stream 305 ₁-305 _(N) is split into M sample sequences 307 ₁₁-307 _(1M), 307 ₂₁-307 _(2M), 307 _(N1)-307 _(NM) at the chip rate. In step 408, the multipath components of each respective sample sequence 307 ₁₁-307 _(1M), 307 ₂₁-305 _(2M), 307 _(N1)-305 _(NM) are combined to generate a respective over-sampled stream 309 ₁₁-309 _(1M), 309 ₂₁-309 _(2M), 309 _(N1)-309 _(NM). In step 410, the over-sampled streams 309 ₁₁-309 _(1M), 309 ₂₁-309 _(2M), 309 _(N1)-309 _(NM) associated with the M sample sequences 307 ₁₁-307 _(1M), 307 ₂₁-307 _(2M), 307 _(N1)-307 _(NM) are combined to generate a combined over-sampled stream 311 ₁-311 _(N). In step 412, the combined over-sampled streams 311 ₁-311 _(N) of the N antennas are combined to generate an antenna diversity sample data stream 314. In step 414, equalization is performed on the antenna diversity sample data stream 314 with an equalizer filter 114 at the chip rate. In step 416, filter coefficients of the equalizer filter are adjusted by adding a filter coefficient correction term 134 to the filter coefficients utilized for a previous iteration. The filter coefficient correction term 134 is generated in accordance with an error signal 131 which is generated by comparing an output from the equalizer filter with a reference signal.

While the present invention has been described in terms of the preferred embodiment, other variations which are within the scope of the invention as outlined in the claims below will be apparent to those skilled in the art. 

1. A code division multiple access (CDMA) receiver comprising: (a) an antenna for receiving signals; (b) a sampler coupled to the antenna and generating a sample data stream at M times chip rate based on the received signals, wherein M is a positive integer; (c) a serial-to-parallel (S/P) converter, the S/P converter being coupled to the sampler for splitting the sample data stream into M sample streams at the chip rate; and (d) a plurality of multipath combiners for combining multipath or delayed replicates of each sample data stream output from the S/P converter.
 2. The receiver of claim 1 wherein M is equal to 2, and the S/P converter splits the sample data stream into an odd sample data stream and an even data sample stream.
 3. A code division multiple access (CDMA) receiver comprising: (a) a plurality of antennas for receiving signals; (b) a plurality of samplers for generating a sample data stream at M times chip rate based on the received signals, wherein M is a positive integer and each sampler is associated with a particular one of the antennas; (c) a plurality of splitters for splitting the sample data stream into M sample sequences at the chip rate, each splitter being coupled to a respective one of the samplers; (d) a plurality of multipath combiners for combining the multipath components of each respective sample sequence to generate a respective over-sampled stream, each multipath combiner being configured to receive a respective one of the over-sampled streams; and (e) a plurality of over-sampling combiners for combining the over-sampled streams associated with the sample sequences generated by a respective one of the splitters into a combined over-sampled stream.
 4. The receiver of claim 3 wherein the splitters are serial-to-parallel (S/P) converters.
 5. An integrated circuit (IC) used in conjunction with a code division multiple access (CDMA) receiver having an antenna for receiving signals, the IC comprising: (a) a sampler coupled to the antenna and generating a sample data stream at M times chip rate based on the received signals, wherein M is a positive integer; (b) a serial-to-parallel (S/P) converter, the S/P converter being coupled to the sampler for splitting the sample data stream into M sample streams at the chip rate; and (c) a plurality of multipath combiners for combining multipath or delayed replicates of each sample data stream output from the S/P converter.
 6. The IC of claim 5 wherein M is equal to 2, and the S/P converter splits the sample data stream into an odd sample data stream and an even data sample stream.
 7. The IC of claim 5 wherein the IC and the CDMA receiver are incorporated in a wireless transmit/receive unit (WTRU).
 8. The IC of claim 5 wherein the IC and the CDMA receiver are incorporated in a base station.
 9. An integrated circuit (IC) used in conjunction with a code division multiple access (CDMA) receiver having N antennas for receiving signals, the IC comprising: (a) a plurality of samplers for generating a sample data stream at M times chip rate based on the received signals, wherein M is a positive integer and each sampler is associated with a particular one of the antennas; (b) a plurality of splitters for splitting the sample data stream into M sample sequences at the chip rate, each splitter being coupled to a respective one of the samplers; (c) a plurality of multipath combiners for combining the multipath components of each respective sample sequence to generate a respective over-sampled stream each multipath combiner being configured to receive a respective one of the over-sampled streams; and (d) a plurality of over-sampling combiners for combining the over-sampled streams associated with the sample sequences generated by a respective one of the splitters into a combined over-sampled stream.
 10. The IC of claim 9 wherein the splitters are serial-to-parallel (S/P) converters.
 11. The IC of claim 9 wherein the IC and the CDMA receiver are incorporated in a wireless transmit/receive unit (WTRU).
 12. The IC of claim 9 wherein the IC and the CDMA receiver are incorporated in a base station. 